The present invention relates to an improvement in a semiconductor memory device having an error correction code (ECC) circuit with a function of detecting and correcting an error in data.
Semiconductor memory devices are becoming increasingly more integrated these days. For this reason, a MOS capacitor in a dynamic memory device must have a small capacity. As a result, the probability of causing a soft error due to alpha rays is high. With the trend for higher integration, the problem of soft errors is also encountered in static memory devices.
As a countermeasure against soft errors, it has been proposed to use an ECC circuit in a memory chip. The ECC circuit performs a parity check of data read out from memory cells. The ECC circuit then corrects the data in accordance with the parity check results. Such an ECC circuit in a memory device is described in, e.g., "Self-Correction Circuit in 1Mb DRAM" in Semiconductors/Transistors, Report of the Institute of Electronics and Communication Engineers of Japan, pp. 51 to 58, particularly with reference to FIG. 11.
For practical reasons ECC circuits most frequently have a configuration facilitating detection and correction of a 1-bit error.
The memory circuit operation must be tested during the die sorting process in the wafer stage or during the burn process, after packaging. In the operation test, the ECC circuit prevents easy detection of hard errors. More specifically, even if a hard error is present, the ECC circuit corrects it. Then, the hard error remains non-detected and reliability of the memory cell is degraded.
In view of this problem, it may be proposed to use an ECC circuit for detecting and correcting an error of 2 bits or more. However, an ECC circuit having a configuration for detecting an error of 2 bits or more is too complicated. It is, therefore, impractical to use a 2-bit ECC circuit in mass-produced memory devices.
When a memory device having an ECC circuit is operated, a memory cell array must be initialized. When the function of the ECC circuit is effective during this initialization, a complex initialization circuit is required. Such a complex initialization circuit adversely influences the performance and reliability of the memory device through its need of a wide element area that serves to reduce the packing density of the memory device.